The present invention relates to differential receivers. More particularly, the present invention relates to sensing when inputs to the differential receiver are not connected to a driving source.
Current electronic systems, such as computer processors, data switches, data storage systems, and the like, must send data back and forth from processor to processor, from data storage systems to processor, or in general, from any electronic unit to another electronic unit that must communicate. For example, a processor may require data that resides on a data storage system such as a hard disk. To get the data, the processor typically sends a request for the data over signal interconnections to the storage system. The request typically contains addressing data and perhaps an amount of data to be retrieved. The storage system receives and interprets the request, retrieves the data from its storage medium (e.g., hard disk), and transmits the data back to the processor.
Performance of the electronic system is highly dependent upon the rate of data transmission between one unit and another unit. In the example of the computer system wherein the processor requires data resident in the storage system, in many cases, the processor is idle until the processor receives the data. Many modern computer processors have more than one task assigned to a processor. In such cases, the processor can usually begin or reawaken other tasks while awaiting data from the storage system for the task requiring data from the storage system. Nonetheless, high-speed data transmission is very important in maximizing throughput in the computer system.
Data is typically routed on electrically conducting signal wires in one of two techniques. A first technique, known as single-ended signaling, uses a single wire for a single signal and references the signal to a voltage supply. Return currents typically flow through a voltage supply plane on a printed wiring board (PWB) or through supply conductors in cabling through which the signal wire is passed. The return currents may be passed through capacitors of suitable capacitance values and suitably low resistive and inductive parasitics from one voltage supply to another, if a single voltage supply cannot be continuously routed near the signal wire.
A receiver of a single-ended signal must compare the voltage of the signal against a voltage referenced to one or more supplies at the receiver. For example, if the signal switches from a first voltage (e.g., ground) to a second voltage (e.g., Vdd), the receiver may interpret a signal voltage exceeding (Vdd-ground)/2 as a logical xe2x80x9c1xe2x80x9d, and a signal voltage less than (Vdd-ground)/2 as a logical xe2x80x9c0xe2x80x9d. Unfortunately, the local supply voltages at the receiver may not be exactly the same as the supply voltages at the driver of the single-ended signal. Supply voltages may in fact be (and usually are, for electronic units physically separated by significant distance) voltage supplies created by different power supplies. Furthermore, local supply xe2x80x9cbouncexe2x80x9d voltage aberrations are caused by switching of large numbers of other signals on a semiconductor chip upon which the driver resides or upon which the receiver resides. All these factors result in significant uncertainty in determining exactly when a single-ended signal is actually interpreted as a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d.
A second signaling technique is called differential signaling. The second technique is typically used in very high-speed signaling, especially when significant distances are involved, and uses two electrical conductors per signal. A first phase of the data, referred to as a positive phase, is sent on a first conductor. A second phase of the data, referred to as a negative phase, is sent on a second conductor. The two phases carry the same data, but are complementary. For example, consider a design wherein an uplevel is 2 volts and a downlevel is 1 volt. A logical xe2x80x9c1xe2x80x9d is on the differential signal when the positive phase is at 2 volts and the negative phase is at 1 volt. When a logical xe2x80x9c0xe2x80x9d is on the differential signal, the positive phase is at 1 volt and the negative phase is at 2 volts. A driver of the differential signal is advantageously designed to cause transitions of the positive phase and the negative phase to occur at substantially the same time and at substantially the same speed (i.e., dV/dt) on the two conductors.
A differential receiver receiving a differential signal does not have to interpret either phase of the differential signal versus a voltage supply at the receiver. Rather, the differential receiver merely needs to determine whether the positive phase or the negative phase is of higher voltage. Differential receivers typically comprise a differential amplifier having suitable xe2x80x9ccommon modexe2x80x9d range to determine whether the differential signal is xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
xe2x80x9cCommon Modexe2x80x9d range denotes the voltage range of the inputs through which the differential amplifier operates properly. For example, suppose that a differential driver drives a 1-volt to 2-volt differential signal. Further suppose that there is a xe2x88x920.5 volt xe2x80x9cground shiftxe2x80x9d between the driver and the receiver, which is to be expected, especially if the driver and the receiver are many meters apart. The receiver would see the signals at 1.5 volts to 2.5 volts due to the shift. The differential receiver, as explained above, simply compares the positive phase voltage to the negative phase voltage. The differential amplifier in the example, however, has to be able to perform the comparison when both signals are 0.5 volt higher than would nominally be expected.
Differential signals are frequently used to transmit data over significant distances, and pluggable cables are often used for the signaling conductors. Pluggable cables create a problem, in that a particular cable may not be plugged in properly. Furthermore, in a particular electronic system, a particular differential receiver may be deliberately left unconnected to any driven differential signal. For example, a particular electronic system may have an electronic unit capable of receiving 16 differential signals in a fully configured system, but sold with only 8 differential signals actually used in a subset configuration, with the other 8 receivers not coupled to driven differential signals. Differential receivers not coupled to driven differential signals should output a predictable logical value, e.g., a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d. Care must be taken to ensure that a differential receiver that is not coupled to a driven differential signal does not oscillate, which could occur if both of the undriven inputs were at substantially the same voltage. Both of the disconnected inputs of a differential receiver are typically coupled together by a terminator, and would therefore be at substantially the same voltage.
A number of techniques exist to ensure that a differential receiver outputs a known logical value when the differential receiver inputs are not coupled to a differential signal. For example, FIG. 1 shows differential receiver 100, having a differential receiver input port comprising inputs INP 107 and INN 108, and comprising differential amplifier 105 coupled to INP 107 and INN 108. A terminator comprising R101 and R102 is shown. Such a terminator is commonly placed between the inputs of a differential receiver to electrically terminate a differential signaling pair of conductors, often referred to as a transmission line. A high-valued pulldown resistor R103 is coupled to the midpoint connection between R101 and R102. The other end of R103 is coupled to a voltage supply xe2x88x92V 109. Pulldown resistor R103 pulls both INP 107 and INN 108 to the voltage of xe2x88x92V 109 when INP 107 and INN 108 are disconnected from a driven differential signal. xe2x88x92V 109, in the example, is less than VREF 110. Comparator 104 detects that a first comparator input, coupled to the midpoint connection between R102 and R103 is below VREF 110 and outputs a logical xe2x80x9c0xe2x80x9d. AND 106 receives an output from differential amplifier 105 and also receives an output from comparator 104. When the output from comparator 104 is at a logical xe2x80x9c0xe2x80x9d, AND 106 drives Out 111 to a logical xe2x80x9c0xe2x80x9d, regardless of the logical value outputted from differential amplifier 105. The circuitry shown in FIG. 1 does output a known logical value when the differential receiver is not connected to a driven differential signal. However, comparator 104 and AND 106 are required. Furthermore, since INP 107 and INN 108 are at substantially the same voltage, differential amplifier 105 may still oscillate, consuming power and driving noise into a power supply grid. AND 106 adds delay to a functional data path from the differential input comprising INP 107 and INN 108 to Out 111.
A second technique practiced in differential receiver art is the circuit shown in FIG. 2. Differential receiver 200 comprises differential amplifier 205 having a first input coupled to INP 207 and a second input coupled to INN 208. Terminating resistor R202 provides the same impedance termination function of the series combination of R101 and R102 in differential receiver 100. In addition, a high-valued resistor R201 is coupled to a voltage supply xe2x88x92V 209 as well as to the first input of differential amplifier 205. A second high-valued resistor R203 is coupled to a second input of differential amplifier 205 and to voltage supply +V 208. When INP 207 and INN 208 are not coupled to a driven differential signal, the circuit of FIG. 2 inserts an offset voltage that ensures that INP 207 and INN 208 are at slightly different voltages, thereby ensuring a known logic level driven on Out 211, and further ensuring that differential amplifier 205 does not oscillate. A drawback of this technique is that the small offset, typically 30-35 mV, degrades the signal margin when a driven differential signal is coupled to the inputs of the differential receiver.
U.S. Pat. No. 6,288,577, by Anthony Wong, teaches a technique similar to the technique shown in FIG. 1. Both inputs of a differential amplifier have high-resistance pullup resistors. Each input to the differential amplifier are further coupled to an input of a comparator; a second input of each comparator is coupled to a reference voltage. An output of each comparator is logically combined with an output of the differential receiver, ensuring a known output logic value if either input, or both inputs, of the differential signal is not coupled to a driving signal. Two extra stages of delay (intrinsic delays of NOR 48 and inverter 52) are shown in the functional path described. Obviously, this could be reduced to only the intrinsic delay of NOR 48, depending on choice of phase.
Therefore, a need exists for an enhanced differential receiver that will output a predetermined logic value and will not oscillate when inputs of the differential receiver are not coupled to a driven differential signal, and when coupled to a driven differential signal, does not degrade signal margin, and incurs substantially no delay beyond the delay of an unenhanced differential receiver in which the delay path consists only of a differential amplifier.
The present invention discloses an enhanced differential receiver that provides a predetermined logical output when the differential receiver input port is not actively driven. The enhanced differential driver has the further advantage of suppressing oscillation when the differential receiver input port is not actively driven. Yet a further advantage is that the enhanced differential receiver has substantially no delay penalty versus a convention differential receiver in which the delay path consists of only a differential amplifier.
In an embodiment, the enhanced differential receiver comprises a differential amplifier further comprising a first active device, having a control port coupled to a first input of the differential receiver, and a second active device having a control port coupled to a second input of the differential receiver. The differential amplifier further comprises a third active device, integrated within the differential amplifier, coupled in parallel with the first device, but having a control port coupled to a reference voltage. In a further embodiment, a fourth active device is coupled in parallel with the second active device, but having a control port coupled to a voltage ensuring that the fourth active device never conducts.
In an exemplary embodiment, all active devices in the differential amplifier are implemented with NPN transistors. In another exemplary embodiment, all active devices in the differential amplifier are implemented with PNP transistors. In yet another exemplary embodiment, all active devices in the differential amplifier are implemented with N-channel Field Effect Transistors (NFETs). In still another exemplary embodiment, all active devices in the differential amplifier are implemented with P-channel Field Effect Transistors (PFETs).